View DS1374U_9103815.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds1374 is a 32-bit binary counter designed to contin-uously count time in seconds. an additional counter gen- erates a periodic alarm or serves as a watchdog timer. if disabled, this counter can be used as 3 bytes of non- volatile (nv) ram. separate output pins are provided for an interrupt and a square wave at one of four selectable frequencies. a precision temperature-compensated refer- ence and comparator circuit monitor the status of v cc to detect power failures, provide a reset output, and auto-matically switch to the backup supply when necessary. additionally, the reset pin is monitored as a pushbutton input for externally generating a reset. the device is pro- grammed serially through an i 2 c serial interface. applications portable instrumentspoint-of-sale equipment medical equipment telecommunications features ? 32-bit binary counter ? second binary counter provides time-of-day alarm, watchdog timer, or nv ram ? separate square-wave and interrupt output pins ? i 2 c serial interface ? automatic power-fail detect and switch circuitry ? single-pin pushbutton reset input/open-drain reset output ? low-voltage operation ? trickle-charge capability ? -40c to +85c operating temperature range ? 10-pin sop, 16-pin so ? available in a surface-mount package with an integrated crystal (ds1374c) ? underwriters laboratories (ul) recognized ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ______________________________________________ maxim integrated products 1 ordering information ds1374 x1 x2 crystal v cc v cc sqw sclsda int rst int rst gnd v backup v cc v cc n.o. pushbutton reset primary battery, rechargeable battery, or super capacitor cpu rpu rpu = t r /c b rpu typical operating circuit 19-5484; rev 4; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range voltage (v) pin-package top mark** ds1374c-18# -40c to +85c 1.8 16 so (300 mils) ds1374c-18 ds1374c-3# -40c to +85c 3.0 16 so (300 mils) ds1374c-3 ds1374c-33# -40c to +85c 3.3 16 so (300 mils) ds1374c-33 DS1374U-18+ -40c to +85c 1.8 10 sop ds1374-18 DS1374U-3+ -40c to +85c 3.0 10 sop ds1374-3 DS1374U-33+ -40c to +85c 3.3 10 sop ds1374-33 pin configurations appear at the end of the data sheet. # denotes a rohs-compliant device that may include lead that is exempt under rohs requirements. the lead finish is jesd97 categor y e3, and is compatible with both lead-based and lead-free soldering processes. + denotes a lead(pb)-free/rohs-compliant package. ** a "#" anywhere on the top mark denotes a rohs-compliant package. a ??anywhere on the top mark denotes a lead(pb)-free package. downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 2 __________________________________________________ ___________________ absolute maximum ratings recommended dc operating conditions (v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc pin relative to ground .....-0.3v to +6.0v voltage range on sda or scl relative to ground ....................................-0.3v to v cc + 0.3v junction-to-ambient thermal resistance ( ja ) (note 1) 16-pin so .....................................................................73?/w 10-pin ?op ...............................................................221?/w junction-to-case thermal resistance ( jc ) (note 1) 16-pin so .....................................................................23?/w 10-pin ?op .................................................................39?/w operating temperature range ...........................-40 c to +85 c storage temperature range .............................-55 c to +125 c lead temperature (soldering, 10s) .................................+260 c soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units ds1374-33 2.97 3.3 5.50 ds1374-3 2.7 3.0 3.3 supply voltage (notes 3, 4) v cc ds1374-18 1.71 1.8 1.89 v input logic 1 v ih (note 3) 0.7 x v cc v cc + 0.3 v input logic 0 v il (note 3) -0.3 +0.3 x v cc v pullup resistor voltage ( int , sqw, sda, scl), v cc = 0v v pu (note 3) 5.5 v ds1374-33 2.70 2.88 2.97 ds1374-3 2.45 2.6 2.7 power-fail voltage (note 3) v pf ds1374-18 1.51 1.6 1.71 v ds1374-33 1.3 3.0 v cc ( max) backup supply voltage (notes 3, 4, 5) v backup ds1374-3, ds1374-18 1.3 3.0 3.7 v note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ __________________ 3 dc electrical characteristics (v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units r1 (note 6) 250 r2 (note 7) 2000 trickle-charge current-limiting resistors r3 (note 8) 4000 input leakage i li (note 9) -1 +1 i/o leakage i lo (note 10) -1 +1 rst pin i/o leakage i lorst (note 11) -200 +1 a sda logic 0 output (v ol = 0.4v) i olsda 3.0 ma v cc > 2v; v ol = 0.4v 3.0 1.71v < v cc < 2v; v ol = 0.2 v cc 3.0 ma rst , sqw, and int logic 0 outputs (note 12) i ol1 1.3v < v cc < 1.71v; v ol = 0.2 v cc 250 a ds1374-18 75 150 ds1374-3 110 200 active supply current (notes 12, 13) i cca ds1374-33 180 300 a ds1374-18 60 100 ds1374-3 80 125 standby current (notes 12, 14) i ccs ds1374-33 115 175 a v backup leakage current (v backup = 3.7v) i backuplkg 100 na dc electrical characteristics ( v cc = 0v, v backup = 3.7v , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions max typ max units v backup current (osc on); sqw off i bkosc1 (note 15) 400 700 na v backup current (osc on); sqw on (32khz) i bkosc2 (notes 15, 16) 600 1000 na v backup data-retention current (osc off) i backupdr 25 100 na downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 4 __________________________________________________ ___________________ ac electrical characteristics (v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) (figure 1) parameter symbol conditions min typ max units fast mode 100 400 scl clock frequency (note 17) f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start conditions t buf standard mode 4.7 s fast mode 0.6 hold time (repeated) start condition (note 18) t hd:sta standard mode 4.0 s fast mode 1.3 low period of scl clock t low standard mode 4.7 s fast mode 0.6 high period of scl clock t high standard mode 4.0 s fast mode 0 0.9 data hold time (notes 19, 20) t hd:dat standard mode 0 0.9 s fast mode 100 data setup time (note 21) t su:dat standard mode 250 ns fast mode 0.6 start setup time t su:sta standard mode 4.7 s fast mode 300 rise time of both sda and scl signals (note 17) t r standard mode 20 + 0.1c b 1000 ns fast mode 300 fall time of both sda and scl signals (note 17) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.7 s capacitive load for each bus line c b (note 17) 400 pf i/o capacitance (sda, scl) c i/o (note 22) 10 pf pulse width of spikes that must be suppressed by the input filter t sp fast mode 30 ns pushbutton debounce pb db (figure 2) 250 ms reset active time t rst (figure 2) 250 ms oscillator stop flag (osf) delay t osf (note 23) 100 ms downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ __________________ 5 power-up/power-down characteristics (t a = -40? to +85?) (figure 3) parameter symbol conditions min typ max units v cc detect to recognize inputs (v cc rising) t rpu (note 24) 250 ms v cc fall time; v pf(max) to v pf(min) t f 300 s v cc rise time; v pf(min) to v pf(max) t r 0 s warning: under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection. note 2: limits at -40? are guaranteed by design and not production tested. note 3: all voltages are referenced to ground. note 4: v backup should not exceed v cc max or 3.7v, whichever is greater. note 5: the use of the 250 trickle-charge resistor is not allowed at v cc > 3.63v and should not be enabled. note 6: measured at v cc = typ, v backup = 0v, register 09h = a5h. note 7: measured at v cc = typ, v backup = 0v, register 09h = a6h. note 8: measured at v cc = typ, v backup = 0v, register 09h = a7h. note 9: scl only. note 10: sda and sqw and int . note 11: the rst pin has an internal 50k pullup resistor to v cc . note 12: trickle charger disabled. note 13: i cca ?cl clocking at max frequency = 400khz. note 14: specified with i 2 c bus inactive. note 15: measured with a 32.768khz crystal attached to the x1 and x2 pins. note 16: wdstr = 1. bbsqw = 1 is required for operation when v cc is below the power-fail trip point (or absent). note 17: c b ?otal capacitance of one bus line in pf. note 18: after this period, the first clock pulse is generated. note 19: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 20: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ihmin of the scl sig- nal) to bridge the undefined region of the falling edge of scl. note 21: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat to 250ns must be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lowperiod of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 22: guaranteed by design. not production tested. note 23: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0v v cc v cc max and 1.3v v backup 3.7v. note 24: this delay applies only if the oscillator is enabled and running. if the eosc bit is 1, the startup time of the oscillator is added to this delay. downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 6 __________________________________________________ ___________________ outputs v cc v pf(max) inputs high-z rst don't care valid recognized recognized valid v pf(min) t rst t rpu t r t f v pf v pf figure 3. power-up/power-down timing t rst pb db rst figure 2. pushbutton reset timing sdascl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 1. data transfer on i 2 c serial bus downloaded from: http:///
i bat0sc1 vs. v bat square-wave off ds1374 toc01 v bat (v) supply current (na) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 350 400 450 500 550300 1.3 v cc = 0v ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output _____________________________________________________________________ 7 typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) i bat0sc2 vs. v bat square-wave on ds1374 toc02 400 450 500 550 600 650 700 750 800350 v cc = 0v v bat (v) supply current (na) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 1.3 i batosc1 vs. temperature v bat = 3.0v ds1374 toc03 temperature ( c) supply current (na) 80 60 40 20 0 -20 400 425 450 475375 -40 v cc = 0v i cca vs. v cc (square-wave on) ds1374 toc04 v cc (v) supply current ( a) 5.3 4.8 3.8 4.3 2.8 3.3 2.3 75 100 125 150 175 200 225 250 275 50 1.8 oscillator frequency vs. v backup ds1374 toc05 v backup (v) frequency (hz) 5.3 4.8 4.3 3.8 3.3 2.8 2.3 1.8 32768.3 32768.4 32768.5 32768.6 32768.7 32768.832768.2 32768.1 32768.0 1.3 v cc = 0v v cc falling vs. rst delay ds1374 toc06 v cc falling (v/ms) reset delay ( s) 10 1 0.10 1 10 100 1000 0.1 0.01 100 v cc = 3.0v to 0v downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 8 __________________________________________________ ___________________ pin description pin sop so name function 1, 2 x1, x2 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. pin x1 is the input to the oscillator and can optionally be connected to an external 32. 768khz osc illator. the output of the internal oscillator, pin x2, is left unconnected if an exte rnal oscillator is connected to pin x1. 3 13 v backup connection for a secondary power supply. this supply is used to operate the oscillator and counters when v cc is absent. supply voltage must be held between 1.3v and 3.7v (-18 and -3) o r 1.3v and 5.5v (-33) for proper operation. this pin can be connected to a prim ary cell such as a lithium cell. additionally, this pin can be connected to a recharg eable cell or a super cap when used with the trickle-charge feature. ul recognized to ensure against rev erse charging when used with a lithium battery. this pin must be grounded if not used. 4 14 rst active-low, open-drain output with a debounced pushbutton input. thi s pin can be activated by a pushbutton reset request, a watchdog alarm condition, or a power-f ail event. it has an internal 50k pullup resistor. no external resistors should be connected. if the crystal oscillator is disabled, the startup time of the oscillator is added to the t rst delay. 5 15 gnd ground 6 16 sda serial data input/output. sda is the input/output for the 2-wire serial interface. the sda pin is open drain and requires an external pullup resistor. 7 1 scl serial clock input. scl is the clock input for the 2-wire serial i nterface and is used to synchronize data movement on the serial interface. 8 2 int interupt. this pin is used to output the alarm interrupt or the watchdog reset sig nal. it is active-low open drain and requires an external pullup resistor. 9 3 sqw square-wave output. this pin is used to output the programmable square-wa ve signal. it is open drain and requires an external pullup resistor. 10 4 v cc dc power for primary power supply 5C12 n.c. no connection. must be connected to ground. clock divider 32-bit counter mux 4.096khz 1hz x1x2 8.192khz 32.768khz 1hz/4.096khz alarm/ watchdog stat/ctrl/ trickle 24-bit counter int control rst control 2-wire interface power control and trickle charge v cc v backup gnd sda scl rst sqw int ds1374 figure 4. functional diagram downloaded from: http:///
detailed description the ds1374 is a real-time clock with an i 2 c serial inter- face. it provides elapsed seconds from a user-definedstarting point in a 32-bit counter (figure 4). a 24-bit counter can be configured as either a watchdog counter or an alarm counter. an on-chip oscillator cir- cuit uses a customer-supplied 32.768khz crystal to keep time. a power-control circuit switches operation from v cc to v backup and back when power on v cc is cycled. the oscillator and counters continue to operatewhen powered by either supply. if a rechargeable backup supply is used, a trickle charger can be enabled to charge the backup supply while v cc is on. oscillator circuit the ds1374 uses an external 32.768khz crystal. theoscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crys- tal parameters for the external crystal. figure 5 shows a functional schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. clock accuracy clock accuracy is dependent upon the accuracy of thecrystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by tempera- ture shifts. external circuit noise coupled into the oscilla- tor circuit can result in the clock running fast. figure 6 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. ds1374c only the ds1374c integrates a standard 32,768hz crystalinto the package. typical accuracy at nominal v cc and 25? is approximately 10ppm. see application note 58 for information about crystal accuracy vs. temperature. ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ __________________ 9 countdown chain x1 x2 c l 1 c l 2 crystal rtc registers ds1374 figure 5. oscillator circuit showing internal bias network local ground plane (layer 2) note: avoid routing signals in the crosshatched area (upper left-hand quadrant) of the package unless there is a ground plane between the signal line and the package. crystal gnd x2 x1 figure 6. layout example parameter symbol min typ max units nominalfrequency f o 32.768 khz seriesresistance esr 45 k loadcapacitance c l 6p f table 1. crystal specifications* * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi- tional specifications . downloaded from: http:///
ds1374 power control the power-control function is provided by a precise,temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written andread when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the regis- ters are maintained from the v backup source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed after rst goes high (figure 1). address map table 3 shows the address map for the ds1374 regis-ters. during a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space (08h). on an i 2 c start, stop, or address pointer incrementing to location 00h, the currenttime is transferred to a second set of registers. these secondary registers read the time information, while the clock continues to run. this eliminates the need to reread the registers in case of an update of the main registers during a read. time-of-day counter the time-of-day counter is a 32-bit up counter thatincrements once per second when the oscillator is run- ning. the contents can be read or written by accessing the address range 00h?3h. when the counter is read, the current time of day is latched into a register, which is output on the serial data line while the counter contin- ues to increment. note: writing to any tod register will reset the 1hz square wave output. i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 10 _________________________________________________ ___________________ supply condition read/write access powered by v cc < v pf , v cc < v backpup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc table 2. power control address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function 00h tod counter byte 0 time-of-day counter 01h tod counter byte 1 time-of-day counter 02h tod counter byte 2 time-of-day counter 03h tod counter byte 3 time-of-day counter 04h wd/ alm counter byte 0 watchdog/alarm counter 05h wd/ alm counter byte 1 watchdog/alarm counter 06h wd/ alm counter byte 2 watchdog/alarm counter 07h eosc wace wd/ alm bbsqw wdstr rs2 rs1 aie control 08h osf 0 0 0 0 0 0 af status 09h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger table 3. address map note: unless otherwise specified, the state of the registers is not defined when power is first applied. downloaded from: http:///
watchdog/alarm counter the contents of the watchdog/alarm counter, which is aseparate 24-bit down counter, are accessed in the address range 04h?6h. when this counter is written, the counter and a seed register are loaded with the desired value. when the counter is to be reloaded, it uses the value in the seed register. when the counter is read, the current counter value is latched into a register, which is output on the serial data line while the counter continues to decrement. iif the counter is not needed, it can be disabled and used as a 24-bit cache of nv ram by setting the wace bit in the control register to logic 0. if all 24 bits of the watchdog/alarm counter are written to zero, the counter is disabled, independent of the wace bit set- ting. when the watchdog counter is is written to a nonzero value, and wace is written to logic 1, the func- tion of the counter is determined by the wd/ alm bit. when the wd/ alm bit in the control register is set to logic 0, the wd/ alm counter decrements every second until it reaches zero. at this point, the af bit in the sta-tus register is set to 1 and the counter is reloaded and restarted. af remains set until cleared by writing it to 0. if aie = 1, the int pin goes active whenever af = 1. wdstr does not affect operation when wd/ alm = 0. when the wd/ alm bit is set to logic 1, the wd/ alm counter decrements every 1/4096 of a second (approx-imately every 244us) until it reaches zero. when any of the watchdog counters bytes are read, the seed value is reloaded and the counter restarts. writing to the watchdog counter updates the seed value and reloads the counter with the new seed value. when the counter reaches zero, the af bit is set and the counter stops. if wdstr = 0, the rst pin pulses low for 250ms, and accesses to the device are inhibited. at the end of the250ms pulse, the af bit is cleared to zero, the rst pin becomes high impedance, and read/write access tothe device is enabled. if wdstr = 1 and the counter reaches zero, the af bitis set and the counter stops. if aie = 0, af remains set until cleared by writing it to 0. if aie = 1, the int pin pulses low for 250ms. at the end of the 250ms pulse,the af bit is cleared and int becomes high impedance. the 250ms pulse on int or rst cannot be truncated by writing either af or aie to zero during the low time. if theint counter is written during the 250ms pulse, the counter starts decrementing upon the pulse completion.the watchdog and alarm function operates from v cc or v bat . when the af bit is set, int is pulled low when the device is powered by v cc or v bat . note: wace must be toggled from logic 0 to logic 1 after the watchdog counter is written from a zero to anonzero value. power-up/power-down reset and pushbutton reset functions a precision temperature-compensated reference andcomparator circuit monitors the status of v cc . when an out-of-tolerance condition occurs, an internal power-failsignal is generated that forces the rst pin low and blocks read/write access to the ds1374. when v cc returns to an in-tolerance condition, the rst pin is held low for 250ms to allow the power supply to stabilize. ifthe eosc bit is set to a logic 1 (to disable the oscillator in battery-backup mode), the reset signal is kept active for250ms plus the startup time of the oscillator. the ds1374 provides for a pushbutton switch to be con- nected to the rst output pin. when the ds1374 is not in a reset cycle, it continuously monitors the rst signal for a low-going edge. if an edge is detected, the ds1374debounces the switch by pulling the rst pin low and inhibits read/write access. after the internal 250ms timerhas expired, the device continues to monitor the rst line. if the line is still low, the ds1374 continues to moni-tor the line, looking for a rising edge. upon detecting release, the ds1374 forces the rst pin low and holds it low for an additional 250ms. ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ _________________ 11 downloaded from: http:///
special purpose registers the ds1374 has two additional registers (07h?8h) thatcontrol the wd/ alm counter and the square-wave, inter- rupt, and reset outputs. control register (07h) bit 7/enable oscillator ( eosc ). when set to logic 0, the oscillator is started. when set to logic 1, the oscilla-tor is stopped. when this bit is set to logic 1, the oscilla- tor is stopped and the ds1374 is placed into a low-power standby mode (i ddr ). this bit is clear (logic 0) when power is first applied. when the ds1374 ispowered by v cc , the oscillator is always on regardless of the state of the eosc bit. bit 6/wd/ a a l l m m counter enable (wace). when set to logic 1, the wd/ alm counter is enabled. when set to logic 0, the wd/ alm counter is disabled, and the 24 bits can be used as nv ram. this bit is clear (logic 0)when power is first applied. bit 5/wd/ a a l l m m counter select (wd/ alm ). when set to logic 0, the counter decrements every second until itreaches zero and is then reloaded and restarted. when set to logic 1, the wd/ alm counter decrements every 1/4096 of a second (approximately every 244?) until itreaches zero, sets the af bit in the status register, and stops. if any of the wd/ alm counter registers are accessed before the counter reaches zero, the counteris reloaded and restarted. this bit is clear (logic 0) when power is first applied. bit 4/battery-backed square-wave enable (bbsqw). this bit, when set to logic 1, enables the square-wave output when v cc is absent and when the ds1374 is being powered by the v backup pin. when bbsqw is logic 0, the sqw pin goes high impedance when v cc falls below the power-fail trip point. this bit is disabled(logic 0) when power is first applied. bit 3/watchdog reset steering bit (wdstr). this bit selects which output pin the watchdog-reset signaloccurs on. when the wdstr bit is set to logic 0, a 250ms pulse occurs on the rst pin if wd/ alm = 1 and the wd/ alm counter reaches zero. the 250ms reset pulse occurs on the int pin when the wdstr bit is set to logic 1. this bit is logic 0 when power is first applied. bits 2, 1/rate select (rs2 and rs1). these bits con- trol the frequency of the square-wave output when thesquare wave has been enabled. table 4 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set (logic 1) when power is first applied. bit 0/alarm interrupt enable (aie). when set to logic 1, this bit permits the alarm flag (af) bit in the statusregister to assert int (when wdstr = 1). when set to logic 0 or wdstr is set to logic 0, the af bit does notinitiate the int signal. if the wd/ alm bit is set to logic 1 and the af flag is set, writing aie to zero does not trun-cate the 250ms pulse on the int pin. the aie bit is at logic 0 when power is first applied. the int output is available while the device is powered by either supply. rs2 rs1 square-wave output frequency 0 0 1hz 0 1 4.096khz 1 0 8.192khz 1 1 32.768khz table 4. square-wave output frequency ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 12 _________________________________________________ ___________________ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc wace wd/ alm bbsqw wdstr rs2 rs1 aie downloaded from: http:///
ds1374 status register (08h) bit 7/oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or wasstopped for some period of time and can be used to judge the validity of the timekeeping data. this bit is set to logic 1 any time the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on both v cc and v backup are insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (i.e., noise, leak- age, etc.). this bit remains at logic 1 until written to logic 0. bit 0/alarm flag (af). a logic 1 in the alarm flag bit indicates that the wd/ alm counter reached zero. if wd/ alm is set to zero and the aie bit = 1, the int pin goes low and stays low until af is cleared. af iscleared when written to logic 0. this bit can only be written to logic 0. attempting to write logic 1 leaves the value unchanged. if wd/ alm is set to 1 and the aie bit = 1, the int pin pulses low for 250ms when the wd/ alm counter reaches zero and sets af = 1. at the pulse completion, the ds1374 clears the af bit to zero.if the 250ms pulse is active, writing af to zero does not truncate the pulse. trickle-charge register (10h) the simplified schematic in figure 7 shows the basiccomponents of the trickle charger. the trickle-charge select (tcs) bits (bits 4?) control the selection of thetrickle charger. to prevent accidental enabling, only a pattern of 1010 enables the trickle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. the diode select (ds) bits (bits 2, 3) select whether or not a diode is connected between v cc and v backup . if ds is 01, no diode is selected; if ds is 10, a diode is selected.the rout bits (bits 0, 1) select the value of the resistor connected between v cc and v backup . table 5 shows the resistor selected by the resistor select (rout) bitsand the diode selected by the diode select (ds) bits. warning: the rout value of 250 must not be select- ed whenever v cc is greater than 3.63v. the user determines diode and resistor selectionaccording to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 3.3v is applied to v cc and a super cap is connected to v backup . also assume the trickle charger has been enabled with adiode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k 1.3ma as the super cap changes, the voltage drop betweenv cc and v backup decreases and therefore the charge current decreases. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 o s f000000a f i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ _________________ 13 tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 function x x x x 0 0 x x disabled x x x x 1 1 x x disabled xxxxxx00 disabled 1 0 1 0 0 1 0 1 no diode, 250 resistor 1 0 1 0 1 0 0 1 one diode, 250 resistor 1 0 1 0 0 1 1 0 no diode, 2k resistor 1 0 1 0 1 0 1 0 one diode, 2k resistor 1 0 1 0 0 1 1 1 no diode, 4k resistor 1 0 1 0 1 0 1 1 one diode, 4k resistor 0 0 0 0 0 0 0 0 power-on reset value table 5. trickle charge register downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 14 _________________________________________________ ___________________ i 2 c serial data bus the ds1374 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitterand a device receiving data is a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must control the bus. the ds1374 operates as a slave on the i 2 c bus. connections to the bus are made through the open-drain i/o lines sda and scl. a standard mode (100khz max clock rate)and a fast mode (400khz max clock rate) are defined within the bus specifications. the ds1374 works in both modes. the following bus protocol has been defined (figure 8): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in thedata line while the clock line is high can be interpret- ed as control signals. stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3?7 figure 8. i 2 c data transfer overview bit 7 tcs3 1 of 16 select note: only 1010b enables charger 1 of 2 select v cc v backup r1 250 tcs 0-3 = trickle charger select ds 0-1 = diode select tout 0-1 = resistor select r2 2k r3 4k 1 of 3 select bit 6 tcs2 bit 5 tcs1 bit 4 tcs0 bit 3 ds1 bit 2 ds0 bit 1 rout1 bit 0 rout0 figure 7. programmable trickle charger downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ _________________ 15 s 1101000 0 a xxxxxxxx a xxxxxxxx a xxxxxxxx a xxxxxxxx p data transferred (x+1 bytes + acknowledge) slave address s - start a - acknowledge p - stop r/w - read/write or direction bit data (n) register address (n) data (n + 1) data (n + x) r/w figure 9. i 2 c write protocol s 1101000 1 a xxxxxxxx a xxxxxxxx a xxxxxxxx a xxxxxxxx /a data transferred (x+1 bytes + acknowledge) slave address s - start a - acknowledge p - stop /a - not acknowledge r/w - read/write or direction bit data (n) data (n + 1) data (n + x) data (n + 2) r/w figure 10. i 2 c read protocol accordingly, the following bus conditions have beendefined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock line ishigh, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line ishigh, defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the dataline is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condi- tion and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited, and is determined by the master device. the informa- tion is transferred byte-wise and each receiver acknowledges with a ninth bit. a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined within the i 2 c bus specifications. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledgeafter the reception of each byte. the master device must generate an extra clock pulse that is associat- ed with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be considered. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enablethe master to generate the stop condition. figures 9 and 10 detail how data transfer is accom-plished on the 2-wire bus. depending on the state of the r/ w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a numberof data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a mas- ter receiver. the master transmits the first byte (the slave address). the slave then returns anacknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?ot acknowledge?is returned. the master device generates the serial clock puls- es and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condi- tion is also the beginning of the next serial transfer, the bus is not released. the ds1374 can operate in the following two modes: slave receiver mode (write mode): serial data and clock data are received through sda and scl.after each byte is received, an acknowledge bit is transmitted. start and stop conditions are rec- ognized as the beginning and end of a serial trans- fer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the master generates a start con- dition. the slave address byte contains the 7-bit ds1374 address, which is 1101000, followed by the direction bit (r/ w ), which is zero for a write. after receiving and decoding the slave addressbyte, the ds1374 outputs an acknowledge on sda. downloaded from: http:///
ds1374 after the ds1374 acknowledges the slave address+ write bit, the master transmits a register address to the ds1374. this sets the register pointer on the ds1374, with the ds1374 acknowledging the trans- fer. the master can then transmit zero or more bytes of data, with the ds1374 acknowledging each byte received. the register pointer increments after each data byte is transferred. the master gen- erates a stop condition to terminate the data write. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiv-er mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the ds1374, while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit ds1374 address, which is 1101000, followed by the direction bit (r/ w ), which is 1 for a read. after receiving and decoding theslave address byte, the ds1374 outputs an acknowledge on sda. the ds1374 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. the ds1374 must receive a not acknowledge to end a read. handling, pc board layout, and assembly the ds1374c package contains a quartz tuning-forkcrystal. pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. ultrasonic cleaning should be avoided to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all no connect (n.c.) pins must be connect- ed to ground. moisture-sensitive packages are shipped from the facto- ry dry-packed. handling instructions listed on the pack- age label must be followed to prevent damage during reflow. refer to the ipc/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output 16 _________________________________________________ ___________________ downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output ___________________________________________________ _________________ 17 chip information process: cmossubstrate connected to ground 1 23 4 5 10 98 7 6 v cc sqwint scl rst v backup x2 x1 top view sda gnd ds1374 sop scl 1 23 4 5 6 7 8 1615 14 13 12 1110 9 sdagnd v backup int v cc sqw n.c.n.c. n.c. n.c. rstn.c. n.c. n.c. n.c. so (0.300") ds1374c pin configurations package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so (0.300? w16#h2 21-0042 90-0107 10 ?op (3.0mm) u10+2 21-0061 90-0330 downloaded from: http:///
ds1374 i 2 c, 32-bit binary counter watchdog rtc with trickle charger and reset input/output maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 8/10 removed leaded parts from the ordering information table; in the absolute maximum ratings section, added the thermal information, lead information, and new no te 1, and updated the soldering information; in the control register (07h) section, corrected the references of intcn to wdstr in the aie bit description; removed the section about the so package reflow in the handling, pc board laout, and assembl section; added the land pattern no. to the package information table 1C5, 12, 16, 17 downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1374U

	To Download DS1374U Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .